1. Field of the Invention
This invention relates to exposure systems for forming integrated circuits on semiconductor wafers. More particularly, the present invention relates to step and repeat exposure systems and a method of increasing the production capability of such systems.
2. Description of the Prior Art
In conventional integrated circuit fabrication, a semiconductor wafer typically undergoes from 4 to 10 major process steps, at each of which steps part of a circuit pattern is exposed from a mask or reticle onto the wafer. In "step-and-repeat" processing, an enlarged mask, typically ten times actual size, contains the circuit pattern for one or a very few individual die sites. The wafer is positioned at one of these die sites, and a reduced image of the mask pattern is exposed onto photoresist covering the wafer through a size reducing system. The wafer is then stepped to the next die site and the mask exposure is repeated. The step-and-repeat operation continues until all die sites have been exposed.
For optimum yield, the pattern images of each subsequent mask must be formed in perfect registration with the circuit elements formed during prior steps. As a minimum, this requires that prior to exposure by each subsequent mask, the wafer must be perfectly located and aligned in the step-and-repeat apparatus, and must be accurately stepped from one die site to the next. Optimally, an individual alignment should be performed at each die site. Such die-by-die alignment is preferred since distortion of the wafer may occur during individual process steps. As a result, although exact uniform spacing existed between the circuit at individual die sites during earlier process steps, the spacing may differ slightly during successive steps. If the wafer is then merely moved a fixed distance from site to site, without individual site alignment, misregistration may occur at some or all of the die sites during exposure of the masks used for these later processing steps.
The speed at which both initial wafer alignment and die-by-die alignment is achieved must be minimized. Step-and-repeat exposure systems are very expensive, typically costing hundreds of thousands of dollars. For cost effective use of such equipment, the time for processing each wafer must be minimized. One way of achieving this is to automate all alignment operations so that no operator intervention is required throughout the entire wafer alignment and step-and-repeat exposure operation.
Techniques for die-by-die alignment have been suggested in the past. Various systems are shown in U.S. Pat. No. 4,052,603 to Karlson and U.S. Pat. No. 4,153,371 to Koizumi, as well as in copending U.S. patent application Ser. No. 238,148 entitled SINGLE LENS REPEATER and assigned to TRE Corporation, the assignee of the present application.
Typically, the initially exposed mask contains both the circuit pattern for the intial processing step and an alignment target which is exposed onto the wafer along with the circuit pattern itself. Typically, this wafer alignment target is exposed in the alley along which the wafer ultimately will be scribed to separate the individual circuit chips.
During the initial processing step the exposed wafer alignment target is subjected to the same processing as the circuit pattern itself. For example, this may comprise the diffusion of an N- or P- type dopant into the semiconductor wafer. In this manner, a die alignment target is formed in the wafer at each die site. It is this alignment target which is used during subsequent mask exposure steps to accomplish die-by-die alignment.
Beginning with the second mask, each mask is provided both with the requisite circuit pattern and with a reticle alignment window or target. This window is a specific distance away from the center of the circuit on the reticle and is outside the normal exposure area of the lens used to expose the circuit pattern onto the wafer. For die-by-die alignment, the wafer is stepped to a target position and appropriate viewing optics are used to view the alignment target on the wafer through the window on the reticle. The position of the target within the window is determined in order to facilitate calculation of the position of the wafer pattern relative to the reticle. After viewing, the wafer must be moved in order to bring the entire pattern within the exposure area of the lens. If the alignment target were viewed precisely at its expected position, this movement is a fixed, predetermined amount which simply compensates for the difference in positioning of the window and alignment target relative to their respective circuit patterns. If the alignment target was viewed at some position other than its expected position, the movement of the wafer is modified in order to correct for any offset. At the end of the movement, the circuit pattern on the reticle is in perfect registration with the pattern on the wafer and an exposure is made.
The wafer is carried on a stage whose position is typically determined by means of laser interferometers. Such interferometers provide extremely precise positional measurements. In prior art systems, the viewing of the alignment target through the window on the reticle is not commenced until the interferometers indicate that the wafer has come to an extremely stable rest at the target position. When stopping at the target position, the stage takes some time to settle precisely at the target position. In order to insure that the wafer has completely settled at the target position, prior art systems wait for a relatively long period of time after the wafer had initially arrived at the target position before viewing the target through the window. Typically, the period between initial arrival of the wafer at the target position and initiation of the acquisition of video data is several tenths of a second.
Due to the extremely high cost of step-and-repeat systems, the throughput of such systems, i.e., the speed at which wafer processing can be accomplished, is critical if cost effectiveness is to be achieved. This is particularly so when die-by-die alignment is done, since alignment of each die necessarily increases the processing time of the system. In order to maintain maximum line resolution in the circuits being formed, the overlapping patterns must be exposed in precise registration. However, it is difficult to maintain such resolution without significantly reducing the throughput of the system. Because each wafer may contain hundreds of die sites, a savings of a few milliseconds in the alignment procedure at each die site can result in a very significant decrease in the overall processing time of the wafer. It is therefore an object of the present invention to increase the throughput of such a system while maintaining precise registration.